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september 2013 doc id 15701 rev 9 1/37 1 vnh5019a-e automotive fully integrated h-bridge motor driver features ecopack ? : lead free and rohs compliant automotive grade: compliance with aec guidelines output current: 30 a 3 v cmos compatible inputs undervoltage and overvoltage shutdown high-side and low-side thermal shutdown cross-conduction protection current limitation very low standby power consumption pwm operation up to 20 khz protection against: ? loss of ground and loss of v cc current sense output proportional to motor current charge pump output for reverse polarity protection output protected against short to ground and short to v cc description the vhn5019a-e is a full bridge motor driver intended for a wide range of automotive applications. the device incorporates a dual monolithic high-side drivers and two low-side switches. the high-side driver switch is designed using stmicroelectronics? well known and proven proprietary vipower ? m0 technology that allows to efficiently integrate on the same die a true power mosfet with an intelligent signal/protection circuit. the three dice are assembled in multipowerso-30 package on electrically isolated lead-frames. this package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. the input signals in a and in b can directly interface to the microcontroller to select the motor direction and the brake condition. the diag a /en a or diag b /en b , when connected to an external pull-up resistor, enable one leg of the bridge. they also provide a feedback digital diagnostic signal. the cs pin allows to monitor the motor current by delivering a current proportional to its value when cs_dis pin is driven low or left open. the pwm, up to 20 khz, lets us to control the speed of the motor in all possible conditions. in all cases, a low-level state on the pwm pin turns-off both the ls a and ls b switches. when pwm rises to a high-level, ls a or ls b turn-on again depending on the input pin state. output current limitation and thermal shutdown protects the concerned high-side in short to ground condition. the short to battery condition is revealed by the overload detector or by thermal shutdown that latches off the relevant low-side. active v cc pin voltage clamp protects the device against low energy spikes in all configurations for the motor. cp pin provides the necessary gate drive for an external n-channel powermos used for reverse polarity protection. type r ds(on) i out v ccmax vnh5019a-e 18 m typ ( per leg) 30 a 41 v multipowerso-30? www.st.com
contents vnh5019a-e 2/37 doc id 15701 rev 9 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.4 waveforms and truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 multipowerso-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.1 thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1.2 thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 multipowerso-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 multipowerso-30 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4 multipowerso-30 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
vnh5019a-e list of tables doc id 15701 rev 9 3/37 list of tables table 1. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. logic inputs (ina, inb, ena, enb,pwm, cs_dis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. switching (v cc = 13 v, r load = 0.87 w, tj = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 10. current sense (8 v < v cc < 21 v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 11. charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12. truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 table 13. truth table in fault conditions (detected on outa). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 14. electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 15. electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 16. electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 17. thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 27 table 18. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. multipowerso-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 20. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
list of figures vnh5019a-e 4/37 doc id 15701 rev 9 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. typical application circuit for dc to 20 khz pwm operation with reverse battery protection (option a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. typical application circuit for dc to 20 khz pwm operation with reverse battery protection (option b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. definition of dynamic cross conduction current during a pwm operation. . . . . . . . . . . . . . 21 figure 11. waveforms in full bridge operation (part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. waveforms in full bridge operation (part 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. definition of delay response time of sense current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 16. multipowerso-30? pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18. auto and mutual rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . 26 figure 19. chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 20. multipowerso-30 hsd thermal impedance junction ambient single pulse . . . . . . . . . . . . 28 figure 21. multipowerso-30 lsd thermal impedance junction ambient single pulse . . . . . . . . . . . . . 28 figure 22. thermal fitting model of an h-bridge in multipowerso-30 . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 23. multipowerso-30 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 24. multipowerso-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 25. multipowerso-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 26. multipowerso-30 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
vnh5019a-e block diagram and pin description doc id 15701 rev 9 5/37 1 block diagram and pin description figure 1. block diagram 287 $ . &+$5*( 3803 32:(5 /,0,7$7,21 )$8/7 '(7(&7,21 2 9 8 9 /6 % b29(57(03(5$7 85( +6 % b29(57(03(5$785( +6 $ b29(57(03(5$785( /6 $ b29(57(03(5$785( /2*,& &/$03b/6 $ '5,9(5 +6 $ &/$03b+6 $ &855(17 /,0,7$7 ,21b$ +6 $ '5,9(5 /6 $ /6 $ *1' $ 29(5/2$' '(7(&725b$ 9 && ',$* $ (1 $ ,1 $ &6 &6b',6 3:0 ,1 % ',$* % (1 % '5,9(5 +6 % +6 % &/$03b+6 % &855(17 /,0,7$7 ,21b% &/$03b/6 % /6 % *1' % '5,9(5 /6 % 29(5/2$' '(7(&725b% 287 % . ("1($'5
block diagram and pin description vnh5019a-e 6/37 doc id 15701 rev 9 figure 2. configuration diagram (top view) table 1. suggested connections for unused and not connected pins connection / pin current sense n.c. outx inputx, pwm diagx/enx cs_dis floating not allowed x x x to ground through 1 k resistor x not allowed through 10 k resistor table 2. pin definitions and functions pin symbol function 1, 25, 30 out a, heat slug2 source of high-side switch a / drain of low-side switch a, power connection to the motor 2,14,17, 22, 24,29 n.c. not connected 3, 13, 23 v cc , heat slug1 drain of high-side switches and connection to the drain of the external powermos used for the reverse battery protection 12 v bat battery connection and connection to the source of the external powermos used for the reverse battery protection 5en a /diag a status of high-side and low-side switches a; open drain output. this pin must be connected to an external pull-up resistor. when externally pulled low, it disables half-bridge a. in case of fault detection (thermal shutdown of a high-side fet or excessive on-state voltage drop across a low-side fet), this pin is pulled low by the device (see table 13: truth table in fault conditions (detected on outa) ) out a out a out a out b out b n.c. v cc in a en a /diag a cs_dis pwm cs en b /diag b in b cp v bat v cc out b n.c. n.c. gnd a gnd a gnd a n.c. v cc n.c. gnd b gnd b gnd b 1 15 16 30 v cc heat slug1 out b heat slug3 out a heat slug2 n.c.
vnh5019a-e block diagram and pin description doc id 15701 rev 9 7/37 ) 6 cs_dis active high cmos compatible pin to disable the current sense pin 4in a clockwise input. cmos compatible 7 pwm pwm input. cmos compatible. 8cs output of current sense. this output delivers a current proportional to the motor current, if cs_dis is low or left open. the information can be read back as an analog voltage across an external resistor. 9en b /diag b status of high-side and low-side switches b; open drain output. this pin must be connected to an external pull up resistor. when externally pulled low, it disables half-bridge b. in case of fault detection (thermal shutdown of a high-side fet or excessive on-state voltage drop across a low-side fet), this pin is pulled low by the device (see table 13: truth table in fault conditions (detected on outa) . 10 in b counter clockwise input. cmos compatible 11 cp connection to the gate of the external mos used for the reverse battery protection 15, 16, 21 out b, heat slug3 source of high-side switch b / drain of low-side switch b, power connection to the motor 26, 27, 28 gnd a source of low-side switch a and power ground (1) 18, 19, 20 gnd b source of low-side switch b and power ground (1) 1. gnda and gndb must be externally connected together table 3. block descriptions (1) name description logic control allows the turn-on and the turn-off of the high-side and the low-side switches according to the table 12 . overvoltage + undervoltage shut down the device outside the range [4.5 v to 24 v] for the battery voltage. high-side, low-side and clamp voltage protect the high-side and the low-side switches from the high-voltage on the battery line in all configuration for the motor. high-side and low-side driver drive the gate of the concerned switch to allow a proper r ds(on) for the leg of the bridge. linear current limiter limits the motor current, by reducing the high-side switch gate-source voltage when short-circuit to ground occurs. high-side and low-side overtemperature protection in case of short-circuit with the increase of the junction?s temperature, it shuts down the concerned driver to prevent its degradation and to protect the die. low-side overload detector detects when low-side current exceeds shutdown current and latches off the concerned low-side. table 2. pin definitions and functions (continued) pin symbol function
block diagram and pin description vnh5019a-e 8/37 doc id 15701 rev 9 charge pump provides the voltage necessary to drive the gate of the external powermos used for the reverse polarity protection fault detection signalizes an abnormal condition of the switch (output shorted to ground or output shorted to battery) by pulling down the concerned enx/diagx pin. power limitation limits the power dissipation of the high-side driver inside safe range in case of short to ground condition. 1. see figure 1 table 3. block descriptions (1) (continued) name description
vnh5019a-e electrical specifications doc id 15701 rev 9 9/37 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality document. v cc in a gnd b i s i outa i ina v ina v cc v outa i sense v outb diag a /en a i ena i gnd i outb in b i inb diag b /en b i enb v enb v ena v inb v sense out a out b pwm cs i pw v pw gnd a gnd cp v bat i bat v bat v cp i cp cs_dis i csd v csd table 4. absolute maximum rating symbol parameter value unit v bat maximum battery voltage (1) -16 +41 v v v cc maximum bridge supply voltage + 41 v i max maximum output current (continuous) 30 a i r reverse output current (continuous) -30 a i in input current (in a and in b pins) +/- 10 ma i en enable input current (diag a /en a and diag b /en b pins) +/- 10 ma i pw pwm input current +/- 10 ma i cp cp output current +/- 10 ma i cs_dis cs_dis input current +/- 10 ma
electrical specifications vnh5019a-e 10/37 doc id 15701 rev 9 2.2 thermal data v cs current sense maximum voltage v cc - 41 +v cc v v v esd electrostatic discharge (human body model: r = 1.5 k , c = 100 pf) 2kv t c case operating temperature -40 to 150 c t stg storage temperature -55 to 150 c 1. this applies with the n-channel mosfet used fo r the reverse battery protection. otherwise v bat has to be shorted to v cc . table 4. absolute maximum rating (continued) symbol parameter value unit table 5. thermal data symbol parameter max. value unit r thj-case thermal resistance junction-case hsd 1.7 c/w thermal resistance junction-case lsd 3.2 c/w r thj-amb thermal resistance junction-ambient see figure 18 c/w
vnh5019a-e electrical specifications doc id 15701 rev 9 11/37 2.3 electrical characteristics values specified in this section are for 8 v < v cc < 21 v, -40 c < t j < 150 c, unless otherwise specified. table 6. power section symbol parameter test conditions min. typ. max. unit v cc operating bridge supply voltage 5.5 24 v i s supply current off-state with all fault cleared and enx = 0 v (standby): in a = in b = pwm = 0; t j = 25 c; v cc = 13 v in a = in b = pwm = 0 off-state (no standby): in a = in b = pwm = 0; enx = 5 v 10 15 60 6 a a ma on-state: in a or in b = 5 v, no pwm in a or in b = 5 v, pwm = 20 khz 48 8 ma ma r onhs static high-side resistance i out = 15 a; t j = 25 c 12.0 m i out = 15 a; t j = - 40 c to 150 c 26.5 r onls static low-side resistance i out = 15 a; t j = 25 c 6.0 m i out = 15 a; t j = - 40 c to 150 c 11.5 v f high-side free-wheeling diode forward voltage i f = 15 a, t j = 150 c 0.6 0.8 v i l(off) high-side off-state output current (per channel) t j = 25 c; v outx = en x = 0 v; v cc = 13 v 3 a t j = 125 c; v outx = en x = 0 v; v cc = 13 v 5 table 7. logic inputs (in a , in b , en a , en b, pwm, cs_dis) symbol parameter test conditions min. typ. max. unit v il low-level input voltage normal operation (diag x /en x pin acts as an input pin) 0.9 v v ih high-level input voltage normal operation (diag x /en x pin acts as an input pin) 2.1 v i inl low-level input current v in = 0.9 v 1 a i inh high-level input current v in = 2.1 v 10 a v ihyst input hysteresis voltage normal operation (diag x /en x pin acts as an input pin) 0.15 v
electrical specifications vnh5019a-e 12/37 doc id 15701 rev 9 v icl input clamp voltage i in = 1 ma 5.5 6.3 7.5 v i in = -1 ma -1.0 -0.7 -0.3 v diag enable low-level output voltage fault operation (diag x /en x pin acts as an output pin); i en = 1 ma 0.4 v table 8. switching (v cc = 13 v, r load = 0.87 , tj = 25 c) symbol parameter test conditions min typ max unit f pwm frequency 0 20 khz t d(on) hsd rise time input rise time < 1s (see figure 9 ) 250 s t d(off) hsd fall time input rise time < 1s (see figure 9 ) 250 s t r lsd rise time (see figure 8 )12s t f lsd fall time (see figure 8 )12s t del delay time during change of operating mode (see figure 7 ) 200 400 1600 s t rr high-side free wheeling diode reverse recovery time (see figure 10 ) 110 ns i rm dynamic cross-conduction current i out = 15 a (see figure 10 ) 2a table 9. protection and diagnostic symbol parameter test conditions min typ max unit v usd v cc undervoltage shutdown 4.5 5.5 v v usdhyst v cc undervoltage shutdown hysteresis 0.5 v v ov v cc overvoltage shutdown 24 27 30 v i lim_h high-side current limitation 30 50 70 a i sd_ls low-side shutdown current 70 115 160 a v clphs (1) high-side clamp voltage (v cc to out a = 0 or out b = 0) i out = 15 a 43 48 54 v v clpls (1) low-side clamp voltage (out a = v cc or out b = v cc to gnd) i out = 15 a 27 30 33 v t tsd (2) thermal shutdown temperature v in = 2.1 v 150 175 200 c table 7. logic inputs (in a , in b , en a , en b, pwm, cs_dis) (continued) symbol parameter test conditions min. typ. max. unit
vnh5019a-e electrical specifications doc id 15701 rev 9 13/37 t tsd_ls low-side thermal shutdown temperature v in = 0 v 150 175 200 c t tr (3) thermal reset temperature 135 c t hyst (3) thermal hysteresis 7 15 c 1. the device is able to pass the esd and is o pulse requirements as specified in the table 15 . 2. t tsd is the minimum threshold temperature between hs and ls 3. valid for both hsd and lsd table 9. protection and diagnostic (continued) symbol parameter test conditions min typ max unit table 10. current sense (8 v < v cc < 21 v) symbol parameter test conditions min typ max unit k 0 i out /i sense i out = 3 a, v sense = 0.5 v, t j = - 40 c to 150c 4670 7110 10110 dk 0 /k 0 analog current sense ratio drift i out = 3 a; v sense = 0.5 v, t j = -40 c to 150 c -19 19 % k 1 i out /i sense i out = 8 a, v sense = 1.3v, t j = - 40 c to 150c 6060 7030 8330 dk 1 /k 1 analog current sense ratio drift i out = 8 a; v sense = 1.3v, t j = -40 c to 150 c -14 14 % k 2 i out /i sense i out = 15 a , v sense = 2.4 v, t j = - 40 c to 150c 6070 6990 7810 dk 2 /k 2 analog current sense ratio drift i out = 15 a; v sense = 2.4 v, t j = -40 c to 150 c -12 12 % k 3 i out /i sense i out = 25 a , v sense = 4 v, t j = - 40 c to 150c 6000 6940 7650 dk 3 /k 3 analog current sense ratio drift i out =25 a; v sense = 4 v, t j = -40 c to 150 c -12 12 % v sense max analog sense output voltage i out = 15 a, r sense = 1.1 k 5v i senseo analog sense leakage current i out = 0 a, v sense = 0 v, v csd = 5 v, v in = 0 v, t j = - 40 to 150c 05 a i out = 0 a, v sense = 0 v, v csd = 0 v, v in = 5 v, t j = - 40 to 150c 0100 t dsenseh delay response time from falling edge of cs_dis pin v in = 5 v, v sense < 4 v, i out = 8 a, i sense = 90% of i sensemax (see fig figure 13 ) 50 s t dsensel delay response time from rising edge of cs_dis pin v in = 5 v, v sense < 4 v, i out = 8 a, i sense = 10% of i sensemax (see fig figure 13 ) 20 s
electrical specifications vnh5019a-e 14/37 doc id 15701 rev 9 2.4 waveforms and truth table in normal operating conditions the diag x /en x pin is considered as an input pin by the device. this pin must be externally pulled-high pwm pin usage: in all cases, a ?0? on the pwm pin turns-off both ls a and ls b switches. when pwm rises back to ?1?, ls a or ls b turn-on again depending on the input pin state. table 11. charge pump symbol parameter test conditions min typ max unit v cp charge pump output voltage en x = 5 v v cc + 5 v cc + 10 v en x = 5 v, v cc = 4.5 v 10.5 i bat charge pump standby current en a = en b = 0 v 200 na table 12. truth table in normal operating conditions in a in b diag a /en a diag b /en b out a out b cs (v csd = 0 v) operating mode 1 1 1 1 h h high imp. brake to v cc 10 1 1 h li sense = i out /k clockwise (cw) 01 1 1 l hi sense = i out /k counterclockwise (ccw) 0 0 1 1 l l high imp. brake to gnd
vnh5019a-e electrical specifications doc id 15701 rev 9 15/37 figure 4. typical application circuit for dc to 20 khz pwm operation with reverse battery protection (option a) m c reg 5v + 5v hs a hs b ls a ls b v bat diag a /en a cs in a pwm out a out b 3.3k 1k 1k 1k 10k 33nf 1.5k v cc v bat d s g cp diag b /en b +5v 1k 3.3k in b 1k gnd a gnd b c note: the external n-channel power mosfet used for the reverse battery protection should have the following characteristics: - bvdss > 20 v (for a reverse battery of -16 v); - r ds(on) < 1/3 of h-bridge total r ds(on) - standard logic gate driving
electrical specifications vnh5019a-e 16/37 doc id 15701 rev 9 figure 5. typical application circuit for dc to 20 khz pwm operation with reverse battery protection (option b) note: in normal operating conditions the diag x /en x pin is considered as an input pin by the device. this pin must be externally pulled high. in case of a fault condition the diag x /en x pin is considered as an output pin by the device. m c reg 5v + 5v hs a hs b ls a ls b v cc diag a /en a cs in a pwm out a out b d s g 3.3k 1k 1k 1k 10k 33nf 1.5k v cc 100k v bat cp diag b /en b +5v 1k 3.3k in b 1k gnd a gnd b c note: the value of the blocking capacitor (c) depends on the application conditions and defines voltage and current ripple onto suppl y line at pwm operation. stored energy of the motor inductance may flyback into the blocking capacitor, if the bridge driver goes into 3-stat e. this causes a hazardous overvoltage if the capacitor is not big enough. as basic orientation, 500 f per 10 a load current is recommended. table 13. truth table in fault conditions (detected on out a ) in a in b diag a /en a diag b /en b out a out b cs (v csd =0v) 1 1 0 1 open h high impedance 0l 0 1hi outb /k 0l high impedance x x 0 open fault information protection action
vnh5019a-e electrical specifications doc id 15701 rev 9 17/37 the fault conditions are: overtemperature on one or both high-sides (for example, if a short to ground occurs as it could be the case described in line 1 and 2 in the ta ble 14 ); short to battery condition on the output (saturation detection on the low-side power mosfet). possible origins of fault conditions may be: out a is shorted to ground. it follows that, high-side a is in overtemperature state. out a is shorted to v cc . it follow that, low-side power mosfet is in saturation state. when a fault condition is detected, the user can know which power element is in fault by monitoring the in a , in b , diag a /en a and diag b /en b pins. in any case, when a fault is detected, the faulty leg of the bridge is latched off. to turn-on the respective output (out x ) again, the input signal must rise from low-level to high-level. figure 6. behavior in fault condition (how a fault can be cleared) note: in case of the fault condition is not removed, the procedure for unlatching and sending the device in stby mode is: - clear the fault in the device (toggle: ina if ena=0 or inb if enb=0) - pull low all inputs, pwm and diag/en pins within tdel. if the diag/en pins are already low, pwm=0, the fault can be cleared simply toggling the input. the device enters in stby mode as soon as the fault is cleared.
electrical specifications vnh5019a-e 18/37 doc id 15701 rev 9 table 14. electrical transient requirements (part 1) iso t/r 7637/1 test pulse test level i ii iii iv delay and impedance 1 -25 v -50 v -75 v -100 v 2 ms, 10 2 +25 v +50 v +75 v +100 v 0.2 ms, 10 3a -25 v -50 v -100 v -150 v 0.1 s, 50 3b +25 v +50 v +75 v +100 v 0.1 s, 50 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 table 15. electrical transient requirements (part 2) iso t/r 7637/1 test pulse test levels i ii iii iv 1c c c c 2c c c c 3a c c c c 3b c c c c 4c c c c 5c e e e table 16. electrical transient requirements (part 3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
vnh5019a-e electrical specifications doc id 15701 rev 9 19/37 2.5 reverse battery protection against reverse battery condition the charge pump feature allows to use an external n-channel mosfet connected as shown in the typical application circuit (see figure 4 ). as alternative option, a n-channel mosfet connected to gnd pin can be used (see typical application circuit in figure figure 5 ). with this configuration we recommend to short v bat pin to v cc . the device sustains no more than -30 a in reverse battery conditions because of the two body diodes of the power mosfets. additionally, in reverse battery condition the i/os of vnh5019a-e is pulled-down to the v cc line (approximately -1.5 v). series resistor must be inserted to limit the current sunk from the microcontroller i/os. if i rmax is the maximum target reverse current through microcontroller i/os, series resistor is: figure 7. definition of the delay times measurement r v ios v cc ? i rmax -------------------------------- = t t v inb v ina, t pwm t i load t del t del
electrical specifications vnh5019a-e 20/37 doc id 15701 rev 9 figure 8. definition of the low-side switching times figure 9. definition of the high-side switching times t f pwm t t v outa, b 20% 90% 80% 10% t r t t v outa v ina, 90% 10% t d(on) t d(off)
vnh5019a-e electrical specifications doc id 15701 rev 9 21/37 figure 10. definition of dynamic cross conduction current during a pwm operation t t i motor pwm t v outb t i cc t rr i rm in a =1, in b =0
electrical specifications vnh5019a-e 22/37 doc id 15701 rev 9 figure 11. waveforms in full bridge operation (part 1) normal operation (diag a /en a =1, diag b /en b =1) in a in b pwm out a out b i outa -> outb diag a /en a diag b /en b diag b /en b in a in b pwm out a out b diag a /en a normal operation (diag a /en a =1, diag b /en b =0 and diag a /en a =0, diag b /en b =1) cs (*) cs i outa -> outb t del t del load connected between out a , out b load connected between out a , out b (*) cs behaviour during pwm mode depends on pwm frequency and duty cycle cs_dis cs_dis in a in b t jhsa diag a /en a diag b /en b i lim t tsd_hsa t tr_hsa t j > t tr current limitation/thermal shutdown or out a shorted to ground cs i outa -> outb normal operation out a shorted to ground normal operation cs_dis t j < t tsd t j =t tsd power limitation limitation current
vnh5019a-e electrical specifications doc id 15701 rev 9 23/37 figure 12. waveforms in full bridge operation (part 2) normal operation out a softly shorted to v cc normal operation undervoltage shutdown in a in b out a out b diag b /en b diag a /en a out a shorted to v cc (resistive short) and undervoltage shutdown cs v outb cs_dis t j_lsa t tsd_ls normal operation out a hardly shorted to v cc normal operation undervoltage shutdown in a in b out a out b diag b /en b diag a /en a out a shorted to v cc (pure short) and undervoltage shutdown cs v outb cs_dis i lsa i sd_ls i lsa i sd_ls t j_lsa t tsd_ls
electrical specifications vnh5019a-e 24/37 doc id 15701 rev 9 figure 13. definition of delay response time of sense current the vnh5019a-e can be used as a high power half-bridge driver achieving an on- resistance per leg of 9.5 m . the figure below shows the suggested configuration: figure 14. half-bridge configuration the vnh5019a-e can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. diag x /en x pins allow to put unused half-bridges in high-impedance. the figure below shows the suggested configuration: current sense input load current cs_dis t dsenseh t dsensel m out a out a out b out b pwm diag a /en a in a diag b /en b in b gnd b gnd a gnd b gnd a pwm diag a /en a in a diag b /en b in b v cc v cc cp cp v bat v bat cs_dis cs_dis
vnh5019a-e electrical specifications doc id 15701 rev 9 25/37 figure 15. multi-motors configuration m 2 out a out a out b out b v cc pwm diag a /en a in a diag b /en b in b gnd b gnd a gnd b gnd a pwm diag a /en a in a diag b /en b in b m 1 m 3 cs_dis cs_dis v cc cp cp v bat v bat
package and pcb thermal data vnh5019a-e 26/37 doc id 15701 rev 9 3 package and pcb thermal data 3.1 multipowerso-30 thermal data figure 16. multipowerso-30? pc board figure 17. chipset configuration figure 18. auto and mutual r thj-amb vs pcb copper area in open box free air condition note: layout condition of rth and zth measurements (pcb fr4 area= 58 mm x 58 mm, pcb thickness=2 mm, cu thickness=35 mm, copper areas: from minimum pad lay-out to 16 cm 2 ). chip 1 r tha chip 2 chip 3 r thb r thc r thab r thac r thbc 0 5 10 15 20 25 30 35 40 45 50 0 2 4 6 8 1012141618 cm 2 of cu area (refer to pcb layout) c/w rtha rthb = rthc rthab = rthac rthbc
vnh5019a-e package and pcb thermal data doc id 15701 rev 9 27/37 3.1.1 thermal calculation in clockw ise and anti-clockwise operation in steady-state mode 3.1.2 thermal calculation in transient mode t hs = p dhs ? z hs + z hsls ? (pd lsa + pd lsb ) + t amb t lsa = pd lsa ? z ls + pd hs ? z hsls + pd lsb ? z hsls + t amb t lsb = pd lsb ? z ls + pd hs ? z hsls + pd ls a ? z hsls + t amb figure 19. chipset configuration equation 1: pulse calculation formula table 17. thermal calculation in clockwise and anti-clockwise operation in steady-state mode chip 1 chip 2 chip 3 tjchip1 tjchip2 tjchip3 on off on p dchip1 ? r tha + p dchip3 ? r thac + t amb p dchip1 ? r thab + p dchip3 ? r thbc + t amb p dchip1 ? r thac + p dchip3 ? r thc + t amb on on off p dchip1 ? r tha + p dchip2 ? r thab + t amb p dchip1 ? r thab + p dchip2 ? r thb + t amb p dchip1 ? r thac + p dchip2 ? r thbc + t amb on off off p dchip1 ? r tha + t amb p dchip1 ? r thab + t amb p dchip1 ? r thac + t amb on on on p dchip1 ? r tha + (p dchip2 + p dchip3 ) ? r thab + t amb pdchip2 ? r thb + p dchip1 ? r thab + p dchip3 ? r thbc + t amb p dchip1 ? r thab + p dchip2 ? r thbc + p dchip3 ? r thc + t amb chip 1 z ls chip 2 chip 3 z ls z ls z hsls z hsls z lsls z th r th z thtp 1 ? () + ? = where t p t ? =
package and pcb thermal data vnh5019a-e 28/37 doc id 15701 rev 9 figure 20. multipowerso-30 hsd thermal impedance junction ambient single pulse figure 21. multipowerso-30 lsd thermal impedance junction ambient single pulse zth -hsd @ cu area 0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000 time (sec) c/w hsd-16 cm^2 cu hsd-8 cm^2 cu hsd-4 cm^2 cu hsd-footprint hslsd-16 cm^2 cu hslsd-8 cm^2 cu hslsd-4 cm^2 cu hslsd-footprint zth -lsd @ cu area 0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000 time (sec) c/w lsd-16 cm^2 cu lsd-8 cm^2 cu lsd-4 cm^2 cu lsd-footprint lslsd-16 cm^2 cu lslsd-8 cm^2 cu lslsd-4 cm^2 cu lslsd-footprint z ls z lsls
vnh5019a-e package and pcb thermal data doc id 15701 rev 9 29/37 figure 22. thermal fitting model of an h-bridge in multipowerso-30 table 18. thermal parameters (1) 1. the blank space means that the val ue is the same as the previous one. area/island (cm 2 ) footprint 4 8 16 r1 = r7 (c/w) 0.1 r2 = r8 (c/w) 0.3 r3 = r10 = r16 (c/w) 0.5 r4 (c/w) 6 r5 (c/w) 30 24 24 24 r6 (c/w) 56 52 42 32 r9 = r15 (c/w) 0.05 r11 = r17 (c/w) 0.7 r12 = r18 (c/w) 10 r13 = r19 (c/w) 36 26 26 26 r14 = r20 (c/w) 56 42 36 28 r21 = r22 (c/w) 35 25 25 25 r23 (c/w) 160 150 150 150 c1 = c7 = c9 = c15 (w.s/c) 0.005 c2 = c8 (w.s/c) 0.01 c3 (w.s/c) 0.03 c4 (w.s/c) 0.4 c5 (w.s/c) 1.5 2 2 2 c6 (w.s/c) 3 4 5 6 c10 = c16 (w.s/c) 0.015 c11 = c17 (w.s/c) 0.05 c12 = c18 (w.s/c) 0.3 c13 = c19 (w.s/c) 1.2 2 2 2 c14 = c20 (w.s/c) 2.5 3 4 5 c21 = c22 = c23 (w.s/c) 0.01 0.008 0.008 0.008
package and packing information vnh5019a-e 30/37 doc id 15701 rev 9 4 package and packing information 4.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.2 multipowerso-30 mechanical data figure 23. multipowerso-30 package dimensions n a2 0.35 a3 l s h x 45 b e a f1 f1 e 30 1 e1 d f3 f2 f2 bottom view c
vnh5019a-e package and packing information doc id 15701 rev 9 31/37 table 19. multipowerso-30 mechanical data symbol data book mm min. typ. max. a 2.35 a2 1.85 2.25 a3 0 0.1 b0.42 0.58 c0.23 0.32 d 17.1 17.2 17.3 e 18.85 19.15 e1 15.9 16 16.1 e1 f1 5.55 6.05 f2 4.6 5.1 f3 9.6 10.1 l 0.8 1.15 n 10 s0 7
package and packing information vnh5019a-e 32/37 doc id 15701 rev 9 4.3 multipowerso-30 suggested land pattern figure 24. multipowerso-30 suggested pad layout
vnh5019a-e package and packing information doc id 15701 rev 9 33/37 4.4 multipowerso-30 packing information the devices can be packed in tube or tape and reel shipments (see table 20: device summary for packaging quantities). figure 25. multipowerso-30 tube shipment (no suffix) figure 26. multipowerso-30 tape and reel shipment (suffix ?tr?) a b c dimension mm base q.ty 29 bulk q.ty 435 tube length ( 0.5) 532 a3.82 b23.6 c ( 0.13) 0.8 reel dimensions so-28 tube shipment (no suffix) dimension mm base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 d (min) 20.2 g (+ 2 / -0) 32 n (min) 100 t (max) 38.4 top cover tape start no components no components components 500 mm min 500 mm min empty components pockets user direction of feed tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 description dimension mm tape width w 32 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 2 hole position f ( 0.1) 14.2 compartment depth k (max) 2.2 hole spacing p1 ( 0.1) 2 end
order codes vnh5019a-e 34/37 doc id 15701 rev 9 5 order codes table 20. device summary package order codes tube tape and reel multipowerso-30 vnh5019a-e vnh5019tr-e
vnh5019a-e revision history doc id 15701 rev 9 35/37 6 revision history table 21. document revision history date revision changes 22-jan-2008 1 initial release. 04-nov-2009 2 uploaded corporate template by using v3 version added table 5: thermal data section 2.1: absolute maximum ratings ? added text table 6: power section ?i s : added max value for in a = in b = pwm = 0; t j = 25 c; v cc =13v in test conditions, deleted in a = in b = pwm = 0 ?v f : changed test conditions, changed typ/max value ?i rm : deleted and copied in table 8: switching (v cc = 13 v, r load = 0.87 w, tj = 25 c) whole row table 8: switching (v cc = 13 v, r load = 0.87 w, tj = 25 c) ?t del : changed min/typ/max value ?copied i rm row by table 6: power section updated table 10: current sense (8 v < v cc < 21 v) table 11: charge pump ?v cp : changed min/max value for en x = 5 v, changed typ value for en x = 5 v, v cc = 4.5 v updated figure 11: waveforms in full bridge operation (part 1) updated figure 12: waveforms in full bridge operation (part 2) added chapter 4 16-dec-2009 3 updated following tables: ? table 6: power section ? table 9: protection and diagnostic ? table 10: current sense (8 v < v cc < 21 v) added figure 6: behavior in fault condition (how a fault can be cleared) added chapter 3: package and pcb thermal data 06-apr-2010 4 updated table 5: thermal data . table 6: power section : ?i s : updated test condition and max value updated table notes on table 9: protection and diagnostic . table 10: current sense (8 v < v cc < 21 v) : ?dk 0 /k 0 , dk 1 /k 1 , dk 3 /k 3 : updated minimum end maximum values. 19-apr-2010 5 updated table 10: current sense (8 v < v cc < 21 v) . 25-may-2010 6 updated features list. updated table 6: power section . 02-sep-2010 7 updated table 5: thermal data .
revision history vnh5019a-e 36/37 doc id 15701 rev 9 22-dec-2011 8 updated figure 1: block diagram added table 1: suggested connections for unused and not connected pins updated table 3: block descriptions table 8: switching (v cc = 13 v, r load = 0.87 w, tj = 25 c) : ?t tsd , t tr , t hyst : added note ?t tsd_ls : added row updated table 13: truth table in fault conditions (detected on outa) updated figure 11: waveforms in full bridge operation (part 1) and figure 12: waveforms in full bridge operation (part 2) 19-sep-2013 9 updated disclaimer. table 21. document revision history (continued) date revision changes
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